Allwinner /D1H /SMHC[1] /SMHC_INTMASK

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Interpret as SMHC_INTMASK

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE_INT_EN)RE_INT_EN 0 (CC_INT_EN)CC_INT_EN 0 (DTC_INT_EN)DTC_INT_EN 0 (DTR_INT_EN)DTR_INT_EN 0 (DRR_INT_EN)DRR_INT_EN 0 (RCE_INT_EN)RCE_INT_EN 0 (DCE_INT_EN)DCE_INT_EN 0 (RTO_BACK_INT_EN)RTO_BACK_INT_EN 0 (DTO_BDS_INT_EN)DTO_BDS_INT_EN 0 (DSTO_VSD_INT_EN)DSTO_VSD_INT_EN 0 (FU_FO_INT_EN)FU_FO_INT_EN 0 (CB_IW_INT_EN)CB_IW_INT_EN 0 (DSE_BC_INT_EN)DSE_BC_INT_EN 0 (ACD_INT_EN)ACD_INT_EN 0 (DEE_INT_EN)DEE_INT_EN 0 (SDIO_INT_EN)SDIO_INT_EN 0 (CARD_INSERT_INT_EN)CARD_INSERT_INT_EN 0 (CARD_REMOVAL_INT_EN)CARD_REMOVAL_INT_EN

Description

Interrupt Mask Register

Fields

RE_INT_EN

Response Error Interrupt Enable

CC_INT_EN

Command Complete Interrupt Enable

DTC_INT_EN

Data Transfer Complete Interrupt Enable

DTR_INT_EN

Data Transmit Request Interrupt Enable

DRR_INT_EN

Data Receive Request Interrupt Enable

RCE_INT_EN

Response CRC Error Interrupt Enable

DCE_INT_EN

Data CRC Error Interrupt Enable

RTO_BACK_INT_EN

Response Timeout/Boot ACK Received Interrupt Enable

DTO_BDS_INT_EN

Data Timeout/Boot Data Start Interrupt Enable

DSTO_VSD_INT_EN

Data Starvation Timeout/V1.8 Switch Done Interrupt Enable

FU_FO_INT_EN

FIFO Underrun/Overflow Interrupt Enable

CB_IW_INT_EN

Command Busy and Illegal Write Interrupt Enable

DSE_BC_INT_EN

Data Start Error Interrupt Enable

ACD_INT_EN

Auto Command Done Interrupt Enable

DEE_INT_EN

Data End-bit Error Interrupt Enable

SDIO_INT_EN

SDIO Interrupt Enable

CARD_INSERT_INT_EN

Card Inserted Interrupt Enable

CARD_REMOVAL_INT_EN

Card Removed Interrupt Enable

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